Comparative Analysis of 4-Bit Multipliers Using Low Power 8-Transistor Full Adder Cells
نویسنده
چکیده
In recent year, power dissipation is one of the biggest challenges in VLSI design. Multipliers are the main sources of power dissipation in DSP blocks. In this project various types of full adders design are performed. Different techniques are used for low power in full adders. The design and power comparison of the low power multiplier using different types of full adder adders units are analyzed. The Vedic multiplier is designed using different types of full adder and the power result is analyzed. The designs are implemented and power results are obtained using TANNER EDA Tool. Tanner SPICE results show that the transistor count and the power required are significantly reduced in the proposed design over the existing design. Keywords-Multipliers, Full adders, CMOS circuit, XOR-XNOR, Low power, Multiplexer, Delay.
منابع مشابه
Symmetrical, Low-Power, and High-Speed 1-Bit Full Adder Cells Using 32nm Carbon Nanotube Field-effect Transistors Technology (TECHNICAL NOTE)
Carbon nanotube field-effect transistors (CNFETs) are a promising candidate to replace conventional metal oxide field-effect transistors (MOSFETs) in the time to come. They have considerable characteristics such as low power consumption and high switching speed. Full adder cell is the main part of the most digital systems as it is building block of subtracter, multiplier, compressor, and other ...
متن کاملPSPICE Implementation of an 8-bit Low Power Energy Recovery Full Adder
Energy recovery technique has attracted interest of low power VLSI designers in recent years. This low power design technique has been proposed and discussed by many researchers. In this paper, we implemented energy recovery technique in the PSPICE using an 8-bit full adder circuit as an example. Full adder circuit has been widely used in arithmetic operations for addition, multipliers and Arit...
متن کاملA High-Speed Dual-Bit Parallel Adder based on Carbon Nanotube FET technology for use in arithmetic units
In this paper, a Dual-Bit Parallel Adder (DBPA) based on minority function using Carbon-Nanotube Field-Effect Transistor (CNFET) is proposed. The possibility of having several threshold voltage (Vt) levels by CNFETs leading to wide use of them in designing of digital circuits. The main goal of designing proposed DBPA is to reduce critical path delay in adder circuits. The proposed design positi...
متن کاملPerformance Analysis of Array Multiplier Using SPL and Control Input Technique Based Adder Cells for Neural Networks
In this article presents the investigation of array multipliers using SPL and control input technique based adder cells. The proposed SPL based adder cell consumes low power, small silicon area and low delay compared to control input technique based adder cell. The proposed circuit is tested with 4 bit array multiplier in terms of power, delay for 45 and 180 nm technology nodes. The array multi...
متن کاملImplementation of Low Power Digital Multipliers using 10 -Transistor Adder Blocks
The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization and optimization of such low power multipliers will aid in comparison and choice of multiplier modu...
متن کامل